DTCP content protection (TSB42AA4 only). A separate document explains the DTCP hardware errata for TSB42AA4. It is available upon request to DTLA licensees only.
Interfaces directly to industry standard 400-, 200-, and 100-Mbps physical layer devices, including Texas Instruments TSB41LV0X and TSB41AXX family of physical layer devices
Compliant with IEEE 1394-1995 and IEEE 1394a-2000 standards
MPEG2 time stamp-based release, as described in IEC 61883-4
High-speed data interface (HSDI):
Byte-wide or serial mode
Two independent HSDI ports
Bidirectional
Several control modes for a variety of applications
Connects seamlessly to common MPEG2 decoder chipsets
16-bit microprocessor interface supports Motorola 68000/68020-style bus
Large 8K-byte FIFO can be configured up to eight independent Tx or Rx FIFOs
8K-byte FIFO supports the following data types:
DVB MPEG2 transport streams (IEC 61883-4)
DirecTVL transport streams
DV program streams (IEC 61883-2)
Asynchronous streams
Support for external processor DMA
Programmable data-/space-available indications for flow control; almost full and almost empty indicators
Supports bus manager functions and automatic 1394 self-ID verification
Interrupt driven to minimize host polling
Single 3.3-V supply
Separate async acknowledge buffer decreases the ack-tracking burden on host
JTAG interface to support post-assembly scan of device I/O
Bus holder isolation
Embedded support for DTCP content protection:
Two M6 baseline ciphers (one per HSDI port)
Random number generator in hardware
SHA-1 secure hash algorithm in hardware
Authentication key cipher in hardware
Optional auto-configuration for MPEG2/DV transmit and receive functions
PID filtering and packet insertion for MPEG2 transport stream
