Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
Members of Texas Instruments Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
Provide Built-In Access to IEEE Std 1149.1 Scan-Accessible Test/Maintenance Facilities at Board and System Levels
While Powered at 3.3 V, the TAP Interface Is Fully 5-V Tolerant for Mastering Both 5-V and/or 3.3-V IEEE Std 1149.1 Targets
Simple Interface to Low-Cost 3.3-V Microprocessors/Microcontrollers Via 8-Bit Asynchronous Read/Write Data Bus
Easy Programming Via Scan-Level Command Set and Smart TAP Control
Transparently Generate Protocols to Support Multidrop TAP Configurations Using TIs Addressable Scan Port
Flexible TCK Generator Provides Programmable Division, Gated-TCK, and Free-Running-TCK Modes
Discrete TAP Control Mode Supports Arbitrary TMS/TDI Sequences for Noncompliant Targets
Programmable 32-Bit Test Cycle Counter Allows Virtually Unlimited Scan/Test Length
Accommodate Target Retiming (Pipeline) Delays of up to 15 TCK Cycles
Test Output Enable (TOE)\ Allows for External Control of TAP Signals
High-Drive Outputs (32-mA IOH, 64-mA IOL) at TAP Support Backplane Interface and/or High Fanout
